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13-17 May 2019
Daejeon, Republic of Korea
Europe/Vienna timezone
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The Implementation and operation of the 4th version of KSTAR Fast Interlock System

15 May 2019, 15:25
2h 35m
Daejeon, Republic of Korea

Daejeon, Republic of Korea

Board: P/1-1
Poster Machine Control, Monitoring, Safety and Remote Manipulation Poster

Speaker

Mr Myungkyu Kim (National Fusion Research Institute)

Description

In order to increase the safety, it is more important than ever to generate a signal to turn off the device even when the abnormal situation occurs during the plasma discharge. KSTAR has built the Fast Interlock System (FIS) since achieving first plasma in 2008, and built and operated the 4th version of FIS which using NI c-RIO technology in 2018 [1].
We moved the safety related functionalities such as heating stop, soft-landing, and etc. of the Central Control System (CCS) built on the existing Versa module Europa bus (VME) to FIS [2]. The EPICS irio driver enables complete control and monitoring of the Field Programmable Gate Array (FPGA), and the distributed interlock information can be integrated in the FIS Input Output Controller (IOC) via Experimental Physics and Industrial Control System (EPICS) [3]. Hardwired signals processed by FPGA are connected to each of dedicated systems, and informational signal is published and subscribed by EPICS.
The FIS Operator Interface (OPI) panel is developed using Control System Studio (CSS), which allows an operator can easily understand FIS operation status and KSTAR shot progress status at a glance. It displays the event occurrence and sequence status on the screen, records event occurrences in the log file, and makes possible to operate with minimal operator’s intervention. The FPGA, which is responsible for signal processing at high speed, implements the event counter logic to record the event occurrence time. The counter values are synchronized with the Central Timing Unit (CTU) start time of 1 second later of shot start and show relevant time from blip 0. The event generated in the FPGA is displayed in 10 microseconds resolution by the 100 kHz operation period. The start-up failure is judged within 250 milliseconds after the plasma discharge. In case of abnormality, generating the fast interlock is the most important function of the fast interlock system. In this paper we will describe the detail implementation and operation results.

  1. M. Kim, et al., “The Implementation of KSTAR Fast Interlock System using c-RIO”, ICALEPCS 2017
  2. J. Hong, et al., “Development and operation of fast protection for KSTAR”, Fusion Eng. Des. 112, 2016
  3. “IRIO EPICS device support-V1.2.0 user’s manual”, UPM, Spain

Primary author

Mr Myungkyu Kim (National Fusion Research Institute)

Co-authors

Mr Tak Taehyun (NFRI) Mr Hong Jaesic (NFRI)

Presentation Materials