Speaker
Description
Software integration of multiple data acquisition and timing hardware devices in Instrumentation and Control and diagnostics applications for fusion environments is very challenging. This is especially relevant for ITER, where the instrumentation is mostly composed of COTS hardware. While the implementation should manage multiple hardware devices from different manufacturers providing different applications program interfaces (APIs), scientists want to use the implementation in different environments such as EPICS, the ITER Real-Time Framework or the MARTe2 middleware as seamlessly as possible.
The Nominal Device Support (NDS) C++ framework under development at ITER for use in its diagnostic applications uses two layers: The NDS-Core layer provides the infrastructure to develop the interfaces with the specific hardware device APIs. Above, the interface layer abstracts and standardizes the specific low-level interfaces of NDS device drivers (developed with NDS-Core) for use with control systems (e.g., EPICS) or real-time applications.
ITER CODAC and its partners have developed NDS device drivers using both PXIe and MTCA platforms for multifunction DAQ devices, timing cards and FPGA-based solutions that are part of the ITER fast controller hardware catalogue. Additional NDS device drivers support communication and archiving through ITER’s high performance networks as well as access to EPICS based systems using the pvAccess protocol.
To support the integration of complex devices and simplify design and maintenance, the NDS approach has been extended with the concept of NDS-Systems. An NDS-System encapsulates a complex structure of multiple NDS device drivers. It implements system-level functions combining functions of the different low-level devices, thereby reducing the number of process variables exposed to the user. It also collects all system-specific logic, keeping it out of the device driver code. The NDS-System implementation provides multiple C++ helpers to aid in driver configuration: High-level methods solve common tasks (data acquisition, time stamping, signal generation, use of digital I/O, etc.) and allow communication on ITER specific and EPICS networks.
| Speaker's Affiliation | Universidad Politecnica de Madrid |
|---|---|
| Member State or IGO | Spain |
