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22-27 October 2018
Mahatma Mandir Conference Centre
Asia/Kolkata timezone

Development of Solid State Power Amplifier for ICH & CD RF Source

26 Oct 2018, 14:00
4h 45m
Mahatma Mandir Conference Centre

Mahatma Mandir Conference Centre

Gandhinagar (nearest Airport: Ahmedabad), India
Poster FIP - Fusion Engineering, Integration and Power Plant Design P8 Posters




ITER-India is developing Ion Cyclotron Heating & Current Drive (ICH&CD) RF source in the frequency of 35 to 65 MHz. Three cascaded amplifiers along with low power RF section, AC/DC power supplies and controls will be used for getting MW level RF power from one source. In the present configuration, two tube based tuned amplifiers, i.e. driver (150 kW) and final (1.7 MW) stage amplifiers are driven by a 10 kW wideband solid state power amplifier (SSPA). Development of such SSPA with required 1.5 dB gain flatness in the above frequency range is very challenging, due to unique design of combiner and output matching circuit. This development is also aiming for achieving compact modular design, higher efficiency, usage of low voltage power supplies and better MTBF value compared with tube based amplifier of similar specification. Since 8 kW is needed as input power to the driver stage amplifier, the design goal for SSPA is to achieve power level of around 10 kW/CW. Multiple pallet amplifier modules having capability of 1 kW are to be combined to achieve desire output. Pallet amplifier module is designed using LDMOS transistors (MRFE6VP61K25H), which is capable to deliver 1000 W CW power in the required frequency range with adequate tune matching circuits. For input matching 9:1 ferrite based balun is used. For output circuit, 1:9 impedance transformation & balance to unbalance quarter wave transformer is used. For gate and drain supply voltages, adequate filters are designed and installed. In this paper, detail design and development of single pallet amplifier module as a part of wideband Solid State Power Amplifier will be discussed along with test results. This paper also include integration and testing of 4 pallet amplifier modules using 4 way power splitter and combiner. Control & monitoring of SSPA will be discussed in brief. Further, upcoming plan for integration of 16 such pallet modules with controls and monitoring system will be discussed. REF: [1] LDMOS transistor Datasheet, [2] Aparajita Mukherjee et. al., Progress in High Power Test of R&D Source for ITER ICRF system, 26th IAEA FEC 2016, 17-22 Oct 2016, Kyoto, Japan
Country or International Organization India
Paper Number FIP/P8-8

Primary author


Mr Akhil Jha (ITER-India) Mrs Aparajita Mukherjee (Institute for Plasma Research) Dr Harikrishna JVS (ITER-India) Mr RAJNISH KUMAR (Scientific Officer-F) Mr Raghuraj Singh (ITER-India) Mr Rajeshkumar Gajanan Trivedi (ITER-India, Institute for Plasma Research)

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